Conventional semiconductor devices generally include a semiconductor substrate, usually a silicon substrate, and a plurality of sequentially formed dielectric layers and conductive paths or interconnects made of conductive materials. Interconnects are usually formed by filling a conductive material in features or cavities etched into the dielectric layers. In an integrated circuit, multiple levels of interconnect networks laterally extend with respect to the substrate surface. Interconnects formed in different layers can be electrically connected using vias or contacts.
The filling of a conductive material into features, such as vias or trenches to form pads, lines, or contacts, can be carried out by electrodeposition. In an electrodeposition or electroplating method, a conductive material, such as copper, is deposited over the substrate surface, including into such features. Then, a material removal technique is typically employed to planarize and remove the excess metal from the top surface, leaving conductors only in the features. The standard material removal technique that is most commonly used for this purpose is chemical mechanical polishing (CMP). Chemical etching, electropolishing (which is also referred to as electroetching or electrochemical etching), and electrochemical mechanical polishing are also attractive process options for copper removal. Copper is the material of choice, at this time, for interconnect applications because of its low resistivity and good electromigration properties.
Standard electroplating techniques yield copper layers that deposit conformally over large features, such as features with widths larger than a few micrometers. This results in a plated wafer surface topography that is not flat. FIG. 1 shows an exemplary structure after a copper plating step. The substrate 10 includes small features 12, such as high aspect ratio trenches or vias, and large trenches 14. The features 12, 14 are formed, e.g., etched into a dielectric layer 16. The substrate 10 is an exemplary portion of a partially fabricated semiconductor wafer. The dielectric layer 16 has a top surface 18. The features 12, 14 and the surface 18 of the dielectric are coated with a barrier and/or adhesion layer 20 and a copper seed layer 22. The barrier layer 20 may be formed of Ta, TaN or combinations of any other materials that are commonly used as barriers to copper migration. The seed layer 22 is deposited over the barrier layer 20, although for specially designed barrier layers there may not be a need for a seed layer. After depositing the seed layer 22, copper is electrodeposited thereon from a suitable plating bath to form the copper layer 24.
During removal of the excess conductor, employing for example a CMP, etching or electropolishing process, the non-flat surface topography of the copper layer 24 is planarized as the excess conductor is removed from the surface, leaving it only within the features and desirably having a flat surface. As described above, standard electroplating techniques yield conformal deposits over large features and non-planar workpiece surfaces that need to be planarized during the excess material removal step. CMP has a tendency, however, to cause “dishing” of the copper surface within larger features 14.
Newly developed electrodeposition techniques, which are collectively called Electrochemical Mechanical Deposition (ECMD) methods, utilize a WSID (workpiece surface influencing device), such as a pad, a polishing pad, a mask or a sweeper in close proximity of the wafer surface during conductor deposition. Action of the WSID during plating gives planar conductor deposits with a flat surface topography even over the largest features present on the workpiece surface. Such a planar deposit is shown as layer 26 in FIG. 1. Removal of excess conductive material, such as copper from such planar deposits, does not require further planarization during the material removal step. Therefore, CMP, electropolishing or electroetching, chemical etching, and electrochemical mechanical polishing techniques may all be successfully employed for removing the overburden in a planar and uniform manner in this case.
Although much progress has been made in electropolishing approaches and apparatuses, there is still a need for electrochemical removal techniques that uniformly planarize and remove excess conductive films from workpiece surfaces. Preferably, such techniques should apply low force on the surface and without causing damage and defects, especially on advanced wafers with low-k materials.